1. Field of the Invention
The present invention relates generally to digital logic circuits, and more specifically, pertains to pipelined designs in digital logic circuits. Multiple-input current-mode logic (CML) gates with a stack height of one are provided by using a composite device wherein input signals are propagated to the output through two or more stages of CML-like primitives connected in succession. A universal three-input CML gate (a 2:1 multiplexor) is provided by using a two-stage pipeline, and can be used to build other logic devices, such as AND, OR, and XOR functions, or a latch. The pipelined CML gates with a stack height of one provide a substantially improved voltage-speed trade-off under low-voltage conditions.
2. Discussion of the Prior Art
Current-mode logic (CML) circuits are commonly used in applications where maximum speed of operation is desired. CML circuits use differential low-voltage signaling and have constant power consumption. A CML gate consists of a dc current source, a differential load and a switching network, composed of either MOSFETs or bipolar transistors, which connect the current source to the differential load. An important parameter of the switching network is its stack height, which is the number of switching devices connected in series between the current source and the load
FIG. 1 illustrates a simple prior art CML buffer gate using a conventional topology.
FIG. 2 illustrates a prior art CML 2:1 multiplexor switching network. In a conventional topology, the switching network routes the tail current from the current source IT to only one of the two load devices R1, R2, and this results in gates with multiple logic inputs having stacked switching devices.
It is becoming increasingly difficult to implement multiple-transistor stacks in newer process generations of circuits, particularly in bipolar technologies, because the supply voltage is being steadily scaled downwardly. The voltage headroom consumed by each stack level either scales much slower than the supply voltage (Vt in CMOS devices), or stays virtually unchanged (Vbe in bipolar devices). In order to implement fast CML circuits at progressively lower supply voltages, it is desirable to reduce the switching stack of multiple-input CML gates to just one transistor.
One possible way to implement CML gates with a single-transistor stack was suggested by Razavi et al. [B. Razavi, Y. Ota, and R. G. Swartz, Design techniques for low-voltage high-speed digital bipolar circuits, IEEE J. Solid-State Circuits, vol. 29, no. 3, March 1994, pp. 332-339] who proposed several ways to “fold” the two-transistor stack of conventional CML gates. These solutions however use different signal levels for different gate inputs, or alternatively use a dc voltage reference input. This requires additional level shifters and reference voltage generators.
A different technique for achieving the same goal was proposed by Campbell et al. [Campbell, Peter M. et al., “A Very-Wide Bandwidth Digital VCO Implemented in GaAs HBTs Using Frequency Multiplication and Division,” 17th Annual GaAs IC Symposium Technical Digest, pp. 311-314, October 1995], who describe an XOR gate built from two cascaded CML-like primitives, each having a single-transistor stack. In contrast to the “folded” CML gates, this approach uses conventional CML signal levels for all inputs and outputs, but the described XOR gate is not a universal logic gate which can be used to build any arbitrary logic function.
In order to describe how the present invention solves the problem of reducing the minimum stack height of CML logic gates, consider the structure of a conventional CML gate. FIG. 1 illustrates a simple prior art CML buffer gate which has one differential input (AP (or A), AN) and one differential output (ZP (or Z), ZN), which simply repeats the input signal. Note that the suffix N (negative) is to show a logical inversion of a signal designated with a P (positive) suffix (e.g. AP) or with no suffix (e.g. A). The same circuit can also function as an inverter if one swaps its outputs (Z′=ZN, ZN′=Z). The CML buffer consists of a tail current source IT, two symmetric switches controlled by differential input signals (AP, AN), and a differential load consisting of two symmetric load devices RL, shown as R1, R2. The switches and the current source can be made from either FETs or bipolar transistors. Nominally only one of the two switches is on, while the other switch is off, so that the tail current flows completely through one of the two loads RL and creates a voltage drop of IT×RL, while the other load RL has no current and no voltage drop. Consequently the outputs ZP, ZN can have only two values: high, equal to the upper power rail voltage VDD; and low, which is VDD−IT×RL. The stack height of this gate is one.
More complex CML logic gates of conventional structure still use one tail current source IT and one symmetric pair of load devices RL, but have a more complex switching tree, and they still route the entire tail current IT to one of the two loads while keeping the other load at zero current. In order to achieve the latter goal, conventional gates use a series connection of switches, and therefore use a stack height of two or more switching devices.
As an illustration, FIG. 2 shows a typical prior art multiple-input CML gate, which is a 2:1 multiplexor (also known as 2:1 selector). It has three logic inputs A, B, and C and one logic output Z (all differential), with the output being equal to A for C=1 and to B for C=0, i.e. Z=A×C+B×CN, and ZN=AN×C+BN×CN. The stack height of this gate is two.
Conventional multiple-transistor-stack CML gates when operated at a progressively lower supply voltage experience a substantial reduction in speed, since there is a minimum amount of voltage per stack level necessary for fast switching. In some cases (but not always) this reduction in speed may be compensated for by an increase in power consumption. Therefore for high-speed, low-power operation under low-voltage conditions, single-transistor-stack CML gates are desirable.
The single-transistor-stack CML gates with “folded” stacks proposed by Razavi et al. use different signal levels for different gate inputs or, alternatively, use a dc voltage reference input. This requires additional level shifters and reference voltage generators, which increase the design complexity.
The single-transistor-stack XOR gate proposed by Campbell et al. is not universal, so there are logical functions that cannot be implemented with this gate, e.g. an AND function.